Analyzing error detection performance of checksums in embedded networks
| dc.contributor.author | Mirza, Ali Naqi | |
| dc.date.accessioned | 2016-10-10T12:02:46Z | |
| dc.date.available | 2016-10-10T12:02:46Z | |
| dc.date.issued | 2016 | |
| dc.description | Submitted in partial fulfillment of the requirements for the Degree of Master of Science in Computer Based Information Systems | en_US |
| dc.description.abstract | Networks are required to transport data from one device to another with adequate precision. For a majority of applications a system is expected to ensure that received data and transmitted data is uniform and consistent. Many elements can change one or more bits of a message sent. Applications therefore need a procedure for the purpose of identification and correction of errors during transmission. Checksums are frequently used by embedded networks for the purpose of identifying errors in data transmission. But decisions regarding which checksum to utilize for error detection in embedded networks are hard to make, since there is an absence of statistics and knowledge about the comparative usefulness of choices available. The aim of this research was to analyze the error detection performance of these checksums frequently utilized: XOR, one‟s complement addition, two‟s complement addition, Adler checksum, Fletcher checksum, and Cyclic Redundancy Check (CRC) and to assess the error detection effectiveness of checksums for those networks which are prepared to give up error detection efficiency in order to curtail costs regarding calculations and computations, for those wanting uniformity between error identification and costs, and finally for those networks which are ready to yield elevated costs for notably enhanced error detection. Even though there is no one size fits all method available, this research gives recommendations in order to decide as to which checksum approach to adopt. A bit flip fault design with manufactured error simulations was utilized for this research. Mathematical technique used for the proposed fault design was Monte Carlo simulations using Mersenne twister random number generator. This study concludes that the error identification performance of XOR, and Adler checksums for arbitrary and autonomous bit and burst errors is below an accepted level, rather 1‟s and 2‟s complement checksums should be utilized for networks prepared to surrender error identification efficiency in order to minimize the cost of calculations. Fletcher checksum should be utilized by networks wanting symmetry between computational costs and error identification and CRCs by networks prepared to yield greater costs of computation for notably enhanced error identification. | en_US |
| dc.identifier.uri | http://hdl.handle.net/11071/4844 | |
| dc.language.iso | en | en_US |
| dc.publisher | Strathmore University | en_US |
| dc.subject | Network | en_US |
| dc.subject | Data | en_US |
| dc.subject | Checksums | en_US |
| dc.subject | embedded networks | en_US |
| dc.title | Analyzing error detection performance of checksums in embedded networks | en_US |
| dc.type | Thesis | en_US |